1. Field of the Invention
This invention relates generally to flash memory cells for use in semiconductor electronic devices and, in particular, to a flash memory EEPROM structure with a split floating gate in a vertical trench.
2. Description of Related Art
There has been a trend in the computer industry to replace disk drives with nonvolatile semiconductor memory. Examples of such memory are electrically programmable and erasable memory devices (EEPROMs) which are generally referred to as flash memory structures. Various types of such memory structures have been disclosed in the prior art, examples of such being the devices disclosed in U.S. Pat. Nos. 5,680,345 and 5,521,505, the former of which discloses a floating gate and control gate in a trench below a silicon substrate surface and the latter of which discloses the floating gate and control gate formed above the silicon surface.
U.S. Pat. Nos. 5,617,351 and 5,656,544 disclose an EEPROM cell which utilizes a split gate, but no common bit line for the split gate. U.S. Pat. No. 5,495,441 discloses a split gate flash memory cell with the control gate in the substrate trench and the floating gate above the surface of the substrate and extending to the spaced source region. U.S. Pat. No. 5,386,132 discloses a split gate EEPROM with vertical floating gates in a trench, but with a control gate spaced apart also in the trench and extending beyond the depth of the floating gate to a buried source region.
In general, split gate flash memory cells have a number of advantages over conventional flash memory cells, such as low voltage power supply operation and over-erase immunity. However, due to their horizontal layout structure, prior art split gate flash memory cells generally have a much larger cell size as compared to conventional flash memory cells. More recent approaches to reduce cell size of split gate flash memory cells is to build a floating gate and bit line vertically above the substrate surface. This approach is disclosed in the publication "A Five V--only Virtual Ground Flash Cell with an Auxiliary Gate for High Density and High Speed Application" by Yamauchi et al. and in U.S. Pat. Nos. 5,479,368, 5,492,846, and 5,640,031. However these split gate configurations require a relatively large surface topography which is created by the upward vertical structure. This structure makes the manufacture of the flash memory cell relatively difficult and complex.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved method of making a flash EEPROM memory cell with a split gate.
It is another object of the present invention to provide a flash memory structure having a floating gate and bit line which is less complex and more easily manufactured than the prior art.
A further object of the invention is to provide a flash memory structure with a floating gate and bit line which reduces the surface topography.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.